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CHL8318 – 8 Phase Digital PWM Controller with SMBus

CHL8318 Preliminary Product Brief (pdf)
CHL8318 Preliminary Product Datasheet (pdf) registered users only

FEATURES

  • Intel VR11.1, VR11.0 compliant Digital PWM controller with SMBus interface
  • Selectable from 1 to 8 phase operation
Parametric Data
  Min Max
Vbias 3.1V 3.5V
Vout 0.5V 2.3V
Fsw 200kHz 1MHz
Iout   >200A
  • Switching frequency configurable from 200kHz to 1MHz
    • Accuracy better than 5% & Ultra low jitter
  • Customized Digital over-clocking features
    • SMBus Gamer command
    • Gamer VID to 2.3V, VID override or track, digital load line adjust
    • Gamer OCP, OVP, OTP, OFF
  • CHiL Efficiency shaping features from light to full load
    • Dynamic Phase Control - 3 programmable regions
    • Variable Gate Drive - gate voltage proportional to output current
  • 1Φ to 4Φ PSI feature improves light load efficiency
  • Designed for use with coupled inductors
  • Current & thermal balancing for each phase
 
  • SMBus fault indicators: OVP, UVP, OCP, OTP
  • SMBus interface for configuring and monitoring current & power
  • Load Line configurable from 0.6mΩ to 1.4mΩ
  • Nine bytes of NVM storage available for customer use
  • Compatabile with CHiL ATL & tri-state MOSFET drivers
  • QFN, lead-free RoHS compliant, MSL Level 1 package 

DESCRIPTION

The CHL8318 supports the PSI and IMON features of VR11.1 for servers and high performance desktop applications. Its customized Digitial Over-clocking features, require no external components. Its SMBus interface can enable Gamer Mode with extended Gamer VID up to 2.3V, digital load line adjust, Gamer Vmax, and faults in Gamer mode.

The CHL8318 deploys unique efficiency shaping features to maintain a flat 90%+ efficient VR across the entire load range.

DPC (Dynamic Phase Control) allows autonomous phase add and drop.

VGD (Variable Gate Drive) optmizes the MOSFET gate drive based on the load current.

PSI can be adjusted from one to four phases for optimized light load efficiency

The unique ATA (Adaptive Transient Algorithm) based on non-linear digital PWM algorithms, uses configuration parameters stored in the internal Non Volatile Memory (NVM) to deliver unmatched fast transient response and accurate steady state behavior for optimized VR component selection and BOM.

Coupled inductor operation allows add/ drop of phases 180º out of phase to improve transient response and form factor.

The CHL8318 supports three NTC temperature sensors to report and trigger VR HOT and OTP faults. Additional features include digital thermal balancing, digital steady state and transient balancing of phase currents and extensive fault configuration and monitoring capability. The CHL8318 includes a unique sensorless and lossless input current monitoring capability.

Design and debug is greatly simplified by use of the CHiL IPD (Intuitive power Designer) GUI to easily access the registers during for a “set-and-forget” approach.

APPLICATIONS

Typical Application
CHL8318 Typical app diagram 
  • Intel® VR11.x CPU VRD and VRM
  • High performance Desktops and Servers
  • DDR memory
  • Overclocking and high efficiency VRs

DESIGN TOOLS

CHiL IPD - The IPD (Intuitive power Designer) is a graphical user interface (GUI) used to assist in multiphase VR designs using the CHL8318 controller. It is a comprehensive tool that encompasses the three key elements of bringing an easy digital VRD design to production: Design, Configuration and Monitoring.

CHL8510 - 6A Synchronous Buck MOSFET Driver with unique CHiL ATL (Active Tri Level) PWM signal for phase shedding

RELATED DEVICES

  • CHL8500 - Synchronous Buck MOSFET Driver with CHiL ATL (Active Tri Level) PWM signal for phase shedding
  • CHL8510 - 6A Synchronous Buck MOSFET Driver with unique CHiL ATL (Active Tri Level) PWM signal for phase shedding

ORDERING INFORMATION

Part # Status Temp (ºC) Package/ Pins Standard quantity RoHS Compliance
CHL8318CRT Active Commercial QFN / 56 Tape & reel, 3000 Y

Further Information

Technical Brief - Diode emulation during load load release (pdf)
Using diode emulation to reduce output voltage overshoot during a transeint load release